Publicacións en colaboración con investigadores/as de Swansea University (26)

2020

  1. Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

    IEEE Access, Vol. 8, pp. 53196-53202

2019

  1. A multi-method simulation toolbox to study performance and variability of nanowire FETs

    Materials, Vol. 12, Núm. 15

  2. Drift-Diffusion Versus Monte Carlo Simulated ON-Current Variability in Nanowire FETs

    IEEE Access, Vol. 7, pp. 12790-12797

  3. Impact of gate edge roughness variability on FinFET and gate-all-around nanowire FET

    IEEE Electron Device Letters, Vol. 40, Núm. 4, pp. 510-513

2018

  1. FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability

    IEEE Journal of the Electron Devices Society, Vol. 6, Núm. 1, pp. 332-340

  2. Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability

    IEEE Transactions on Electron Devices, Vol. 65, Núm. 2, pp. 456-462

  3. Spatial Sensitivity of Silicon GAA Nanowire FETs under Line Edge Roughness Variations

    IEEE Journal of the Electron Devices Society, Vol. 6, pp. 601-610

2017

  1. Fluctuation Sensitivity Map: A Novel Technique to Characterise and Predict Device Behaviour Under Metal Grain Work-Function Variability Effects

    IEEE Transactions on Electron Devices, Vol. 64, Núm. 4, pp. 1695-1701

  2. Metal Grain Granularity Study on a Gate-All-Around Nanowire FET

    IEEE Transactions on Electron Devices, Vol. 64, Núm. 12, pp. 5263-5269

  3. Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations

    Solid-State Electronics, Vol. 128, pp. 17-24

2016

  1. Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

    IEEE Transactions on Electron Devices, Vol. 63, Núm. 3, pp. 1209-1216

  2. Impact of cross-section of 10.4 nm gate length Ino.53Gao.47As FinFETs on metal grain variability

    International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

  3. Scaling/LER study of Si GAA nanowire FET using 3D Finite Element Monte Carlo simulations

    2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2016

  4. Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes

    Semiconductor Science and Technology, Vol. 31, Núm. 7

  5. Study of Metal-Gate Work-Function Variation Using Voronoi Cells: Comparison of Rayleigh and Gamma Distributions

    IEEE Transactions on Electron Devices, Vol. 63, Núm. 6, pp. 2625-2628

2015

  1. Implementation of numerical methods for nanoscaled semiconductor device simulation using OpenCL

    Proceedings of the 2015 10th Spanish Conference on Electron Devices, CDE 2015

  2. Variability characterisation of nanoscale Si and InGaAs fin field-effect-transistors at subthreshold

    Journal of Low Power Electronics, Vol. 11, Núm. 2, pp. 256-262

2014

  1. Influence of device geometry on electrical characteristics of a 10.7 nm SOI-FinFET

    2014 International Workshop on Computational Electronics, IWCE 2014

  2. Random dopant, line-edge roughness, and gate workfunction variability in a nano InGaAs finFET

    IEEE Transactions on Electron Devices, Vol. 61, Núm. 2, pp. 466-472

  3. Scaling of metal gate workfunction variability in nanometer SOI-FinFETs

    ULIS 2014 - 2014 15th International Conference on Ultimate Integration on Silicon