Publications by the researcher in collaboration with GUILLERMO INDALECIO FERNANDEZ (19)

2020

  1. Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

    IEEE Access, Vol. 8, pp. 53196-53202

2019

  1. A multi-method simulation toolbox to study performance and variability of nanowire FETs

    Materials, Vol. 12, Núm. 15

  2. Drift-Diffusion Versus Monte Carlo Simulated ON-Current Variability in Nanowire FETs

    IEEE Access, Vol. 7, pp. 12790-12797

  3. Impact of gate edge roughness variability on FinFET and gate-all-around nanowire FET

    IEEE Electron Device Letters, Vol. 40, Núm. 4, pp. 510-513

  4. Impact of threshold voltage extraction methods on semiconductor device variability

    Solid-State Electronics, Vol. 159, pp. 165-170

2018

  1. FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability

    IEEE Journal of the Electron Devices Society, Vol. 6, Núm. 1, pp. 332-340

  2. FoMPy: A figure of merit extraction tool for semiconductor device simulations

    2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018

  3. Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability

    IEEE Transactions on Electron Devices, Vol. 65, Núm. 2, pp. 456-462

2017

  1. Metal Grain Granularity Study on a Gate-All-Around Nanowire FET

    IEEE Transactions on Electron Devices, Vol. 64, Núm. 12, pp. 5263-5269

  2. Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations

    Solid-State Electronics, Vol. 128, pp. 17-24

2016

  1. Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

    IEEE Transactions on Electron Devices, Vol. 63, Núm. 3, pp. 1209-1216

  2. Scaling/LER study of Si GAA nanowire FET using 3D Finite Element Monte Carlo simulations

    2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2016

  3. Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes

    Semiconductor Science and Technology, Vol. 31, Núm. 7

2015

  1. A tool to deploy nanodevice simulations on cloud

    Proceedings of the 2015 10th Spanish Conference on Electron Devices, CDE 2015

  2. Design and Monte Carlo Simulation of a LED-Based Optic Coupler

    Proceedings - UKSim-AMSS 17th International Conference on Computer Modelling and Simulation, UKSim 2015

2014

  1. Influence of device geometry on electrical characteristics of a 10.7 nm SOI-FinFET

    2014 International Workshop on Computational Electronics, IWCE 2014

  2. Random dopant, line-edge roughness, and gate workfunction variability in a nano InGaAs finFET

    IEEE Transactions on Electron Devices, Vol. 61, Núm. 2, pp. 466-472

2013

  1. Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In0.53 Ga 0.47 As GAA MOSFET

    IEEE Electron Device Letters, Vol. 34, Núm. 2, pp. 205-207

2012

  1. 3D simulations of random dopant induced threshold voltage variability in inversion-mode In0.53Ga0.47As GAA MOSFETs

    International Conference on Simulation of Semiconductor Processes and Devices, SISPAD