GUILLERMO
INDALECIO FERNANDEZ
Investigador en el periodo 2017-2019
DANIEL
NAGY
Profesor ayudante doctor
Publicaciones en las que colabora con DANIEL NAGY (13)
2020
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Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
IEEE Access, Vol. 8, pp. 53196-53202
2019
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A multi-method simulation toolbox to study performance and variability of nanowire FETs
Materials, Vol. 12, Núm. 15
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Drift-Diffusion Versus Monte Carlo Simulated ON-Current Variability in Nanowire FETs
IEEE Access, Vol. 7, pp. 12790-12797
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Impact of gate edge roughness variability on FinFET and gate-all-around nanowire FET
IEEE Electron Device Letters, Vol. 40, Núm. 4, pp. 510-513
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Impact of threshold voltage extraction methods on semiconductor device variability
Solid-State Electronics, Vol. 159, pp. 165-170
2018
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FinFET versus gate-all-around nanowire FET: Performance, scaling, and variability
IEEE Journal of the Electron Devices Society, Vol. 6, Núm. 1, pp. 332-340
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FoMPy: A figure of merit extraction tool for semiconductor device simulations
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2018
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Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability
IEEE Transactions on Electron Devices, Vol. 65, Núm. 2, pp. 456-462
2017
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Metal Grain Granularity Study on a Gate-All-Around Nanowire FET
IEEE Transactions on Electron Devices, Vol. 64, Núm. 12, pp. 5263-5269
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Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations
Solid-State Electronics, Vol. 128, pp. 17-24
2016
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Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs
IEEE Transactions on Electron Devices, Vol. 63, Núm. 3, pp. 1209-1216
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Scaling/LER study of Si GAA nanowire FET using 3D Finite Element Monte Carlo simulations
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2016
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Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes
Semiconductor Science and Technology, Vol. 31, Núm. 7