Publicaciones (19) Publicaciones de ALVARO VAZQUEZ ALVAREZ

2024

  1. MPI4All: Universal Binding Generation for MPI Parallel Programming

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2019

  1. Fast ground filtering of airborne LiDAR data based on iterative scan-line spline interpolation

    Remote Sensing, Vol. 11, Núm. 19

  2. New 3D Projection Transformation for Point Clouds

    Proceedings - Symposium on Computer Arithmetic

2017

  1. A number system approach for adder topologies

    Proceedings - 24th IEEE Symposium on Computer Arithmetic, ARITH 2017

  2. A sum error detection scheme for decimal arithmetic

    Proceedings - 24th IEEE Symposium on Computer Arithmetic, ARITH 2017

2014

  1. Fast radix-10 multiplication using redundant BCD codes

    IEEE Transactions on Computers, Vol. 63, Núm. 8, pp. 1902-1914

2013

  1. Iterative algorithm and architecture for exponential, logarithm, powering, and root extraction

    IEEE Transactions on Computers, Vol. 62, Núm. 9, pp. 1721-1731

2012

  1. Redundant floating-point decimal CORDIC algorithm

    IEEE Transactions on Computers, Vol. 61, Núm. 11, pp. 1551-1562

2011

  1. Composite iterative algorithm and architecture for q-th root calculation

    Proceedings - Symposium on Computer Arithmetic

2010

  1. Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs

    Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10

  2. Improved design of high-performance parallel decimal multipliers

    IEEE Transactions on Computers, Vol. 59, Núm. 5, pp. 679-693

  3. Multi-Operand Decimal Addition by Efficient Reuse of a Binary Carry-Save Adder Tree

    2010 CONFERENCE RECORD OF THE FORTY FOURTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS (ASILOMAR)

  4. Multi-operand decimal addition by efficient reuse of a binary carry-save adder tree

    Conference Record - Asilomar Conference on Signals, Systems and Computers

2009

  1. A high-performance significant BCD adder with IEEE 754-2008 decimal rounding

    Proceedings - Symposium on Computer Arithmetic

  2. Computation of decimal transcendental functions using the cordic algorithm

    Proceedings - Symposium on Computer Arithmetic

2008

  1. New insights on ling adders

    Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

2007

  1. A new family of high - Performance parallel decimal multipliers

    Proceedings - Symposium on Computer Arithmetic

  2. A radix-10 SRT divider based on alternative BCD codings

    2007 IEEE International Conference on Computer Design, ICCD 2007

2003

  1. Implementation of the exponential function in a floating-point unit

    Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Vol. 33, Núm. 1-2, pp. 125-145