Figures of merit that characterize silicon gate-all-around nanowire FETs affected by line edge roughness variability
- Garcia-Loureiro, Antonio 1
- Seoane, Natalia 1
- Fernandez, Julian G. 1
- Comesaña, Enrique 1
- Pichel, Juan C. 1
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1
Universidade de Santiago de Compostela
info
Editor: Zenodo
Ano de publicación: 2023
Tipo: Dataset
DOI:
10.5281/ZENODO.7674908
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Resumo
Off-current, threshold voltage, sub-threshold slope and on-current values for two silicon gate-all-around nanowire FETs affected by line edge roughness (LER) variability, a 22 nm gate length device and a 10 nm gate length one. The LER profile that characterizes the roughness deformation is also included in the dataset. Different correlation length (CL) and root mean square (RMS) heights values are characterized.