Publicacións (10) Publicacións nas que participase algún/ha investigador/a Ver datos de investigación referenciados.

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2005

  1. 3D parallel simulation of InP/InGaAs HBT

    2005 Spanish Conference on Electron Devices, Proceedings

  2. A new technique to reduce false sharing in parallel irregular codes based on distance functions

    Proceedings of the International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN

  3. A one-quadrant discrete-Time cellular neural network architecture for pixel-Level snakes: B/W processing

    Proceedings - IEEE International Symposium on Circuits and Systems

  4. A one-quadrant discrete-time cellular neural network CMOS chip for pixel-level snakes

    Proceedings - IEEE International Symposium on Circuits and Systems

  5. On the emulation of large-neighborhood templates with binary cnn-based architectures

    Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications

  6. Parallel complete remeshing for adaptive schemes

    International Journal of Computational Science and Engineering, Vol. 1, Núm. 2-4, pp. 207-215

  7. Performance optimization of irregular codes based on the combination of reordering and blocking techniques

    Parallel Computing, Vol. 31, Núm. 8-9, pp. 858-876

  8. Robustness improvement in binary cellular non-linear network architectures

    Proceedings of the 2005 European Conference on Circuit Theory and Design

  9. Robustness improvement in binary cellular non-linear network architectures

    PROCEEDINGS OF THE 2005 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN, VOL 1

  10. Runtime characterisation of irregular accesses applied to parallelisation of irregular reductions

    International Journal of Computational Science and Engineering, Vol. 1, Núm. 1, pp. 1-14