Publicacións (68) Publicacións nas que participase algún/ha investigador/a Ver datos de investigación referenciados.

filter_list Hardware and Architecture

2024

  1. Assessing Intel OneAPI capabilities and cloud-performance for heterogeneous computing

    Journal of Supercomputing, Vol. 80, Núm. 9, pp. 13295-13316

2023

  1. Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL

    Journal of Supercomputing, Vol. 79, Núm. 9, pp. 9866-9888

2022

  1. CIMAR, NIMAR, and LMMA: Novel algorithms for thread and memory migrations in user space on NUMA systems using hardware counters

    Future Generation Computer Systems, Vol. 129, pp. 18-32

2021

  1. A new AXT format for an efficient SpMV product using AVX-512 instructions and CUDA

    Advances in Engineering Software, Vol. 156

2019

  1. Influence of architectural features of the SNC-4 mode of the Intel Xeon Phi KNL on matrix multiplication

    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

2017

  1. A number system approach for adder topologies

    Proceedings - 24th IEEE Symposium on Computer Arithmetic, ARITH 2017

2016

  1. PRECISION: A Reconfigurable SIMD/MIMD Coprocessor for Computer Vision Systems-on-Chip

    IEEE Transactions on Computers, Vol. 65, Núm. 8, pp. 2548-2561

  2. Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes

    Semiconductor Science and Technology, Vol. 31, Núm. 7

2015

  1. Reconfigurable computing for future vision-capable devices

    Proceedings - 2015 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2015

2014

  1. 3DyRM: a dynamic roofline model including memory latency information

    Journal of Supercomputing, Vol. 70, Núm. 2, pp. 696-708

  2. A hardware counter-based toolkit for the analysis of memory accesses in SMPs

    Concurrency Computation Practice and Experience, Vol. 26, Núm. 6, pp. 1328-1341

  3. Fast radix-10 multiplication using redundant BCD codes

    IEEE Transactions on Computers, Vol. 63, Núm. 8, pp. 1902-1914

  4. Modeling the performance of parallel applications using model selection techniques

    Concurrency Computation Practice and Experience, Vol. 26, Núm. 2, pp. 586-599

  5. Using an extended Roofline Model to understand data and thread affinities on NUMA systems

    Annals of Multicore and GPU Programming: AMGP, Vol. 1, Núm. 1, pp. 56-67

2013

  1. A flexible and dynamic page migration infrastructure based on hardware counters

    Journal of Supercomputing, Vol. 65, Núm. 2, pp. 930-948

  2. Extensión del modelo Roofline y herramientas para su uso

    Actas de las XXIV Jornadas de Paralelismo

  3. Nanodevice simulations on CloudStack

    Proceedings of the 2013 Spanish Conference on Electron Devices, CDE 2013

  4. Partitioning and mapping a fast level-set algorithm on the GPU

    Proceedings of the 2013 IEEE 7th International Conference on Intelligent Data Acquisition and Advanced Computing Systems, IDAACS 2013

  5. Sparse matrix-vector multiplication on the Single-Chip Cloud Computer many-core processor

    Journal of Parallel and Distributed Computing, Vol. 73, Núm. 12, pp. 1539-1550

2012

  1. A graphical tool for performance analysis of multicore systems based on the Roofline Model

    Proceedings of the 2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012